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Tahrina Ahmed, Ph.D., Director, Cadence Design Systems

 


Tahrina Ahmed is a director at Cadence. She is an experienced computer architect, excellent technical manager with outstanding leadership abilities, able to coordinate and direct all phases of project-based efforts while managing, motivating and leading teams. She provides strategic insight and landing zones for roadmap planning and design wins. She also identifies value propositions for upcoming technologies and opportunities to introduce new cutting-edge projects across different Business Units.


In the past, Tahrina was a Principal CPU Architect and Sr. Engineering Manager at AMD where she led the cross-geographical CPU performance architecture team towards the vision of achieving best-of-class performance and determining future roadmap. She has also worked for Intel as Software Engineering Manager. She was at Cisco as ASIC design Engineer.


Tahrina obtained her PhD and Master's degree in Electrical Engineering from Stanford University. She obtained her Bachelor's degree in EE from San Jose State University.



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